How to use make command in Linux.

How To Use Make Command In Linux.

This article will show you how to use the Linux make command with examples.

The Linux make command is a commonly used utility by sysadmins and developers. The command assists in the compilation process and is a must-have tool for building large applications. This utility cuts out repetition and speeds up compilation, saving time.


How Does the make Command Work?

The make command compiles different program pieces and builds a final executable. The purpose of make is to automate file compilation, making the process simpler and less time-consuming. 

The command works with any programming language as long as the compiler can be executed with a shell command.

Compiling is straightforward when working with a few files. Therefore, the process includes invoking the compiler and listing file names.

Invoke the compiler with:

gcc file1.c file2.c file3.h

The gcc command creates an a.out file, which is a standard compiled executable.

However, changing one of the source files requires recompiling everything, which is even more complicated when working with large apps. The make command automates the process, allowing users to update only pieces that need to be changed without recompiling every file.

The make command uses a user-generated file, Makefile, to compile program pieces. When executed for the first time, make searches the Makefile for instructions, e.g., file descriptions and modification times. Based on the available data, make decides which files need to be updated and issues the necessary commands.


What Are Makefiles?

A Makefile is a text file containing a set of rules that instructs make how to build an application. A rule consists of three parts: the target, dependencies, and command(s).

The Makefile basic syntax is:

target: dependencies
<TAB> commands

Parts of the syntax are:

  • Targets. Names of the files to be created or updated after executing make.

  • Dependencies. Names of the files (separated by spaces) from which the target is constructed.

  • The commands. Rules describing how to create or update the target when dependencies change.

One Makefile has several sets of rules. The first rule is the default one and states how the final executable (the target) is to be made from not-yet-created object files (dependencies).

The syntax in this case is:

EXECUTABLE: Object file 1, Object file 2
<TAB> commands

After setting rule one, the user adds instructions on how to create object files.

The make command works by compiling source files into object files and then compiling object files into the target file, the final executable. The Makefile syntax with the three rules mentioned above is:

EXECUTABLE: Object file 1, Object file 2
<TAB> commands

Object file 1: Source file 1, Source file 2
<TAB> commands

Object file 2: Source file 2
<TAB> commands


Linux make Command Syntax

The basic make syntax looks like this:

make [OPTIONS]

When executed without arguments, make builds the first target from the Makefile.


Linux make Command Options

The make command is widely used due to its effectiveness, variety, and the ability to perform specific actions. While the command prints result when run without options, adding arguments expands make‘s usability.

Here are the most used options:



-B, –always-make

Unconditionally compiles all targets.

-d, –debug[=FLAGS]  

Prints the debugging information.

-C dir, –directory=dir  

Changes the directory before executing the Makefile.

-f file, –file=file, –Makefile=FILE  

Uses a specific file as a Makefile.

-i, –ignore-errors  

Ignores all errors in commands.

-I dir, –include-dir=dir  

Specifies a directory to search for the specified Makefile.

-j [jobs], –jobs[=jobs]  

Specifies the number of jobs to run simultaneously.

-k, –keep-going  

Continues running make for as long as possible after getting an error.

-l [load], –load-average[=load]  

Specifies that no new task should be started if other tasks are in the queue.

-n, –dry-run, –just-print, –recon  

Prints expected output without executing make.

-o file, –old-file=file, –assume-old=file  

Ensures that make does not remake the file even if it is older than the dependencies.

-p, –print-data-base

Prints the database produced after reading the Makefile.

-q, –question  

Activates the Question mode, in which make doesn’t run any commands but returns an exit status zero if the target is already compiled.

-r, –no-builtin-rules  

Eliminates the built-in implicit rules.

-s, –silent, –quiet  

Restricts printing the commands as they are executed.

-S, –no-keep-going, –stop  

Stops “-k, –keep-going” command.

-t, –touch  

Touches files instead of running the commands.


Traces each target’s disposition.

-W file, –what-if=file, –new-file=file, –assume-new=file  

Ignores the fact that the target file has been modified.


Warns that an unknown variable is referenced.


Linux make Command Examples

The best way to understand make and Makefiles is by running the command and different options on a simple program.

For example, to build an executable that prints the message “Learn about Makefiles”, follow these steps:

  1. Create a directory called


  1. Make three source files

main.c, text.c, and text.h.

  • main.c – is the file with the main function (int main) that calls a function from another file.

  • text.c – is the file with the you want to print “Learn about Makefiles!”.

  • text.h  – is the header file with declarations for the functions. The header is included in both c files with the #include argument, which has the same purpose as copy/pasting the header’s contents.


Create a Program

There are two ways to create a program:

  • Compiling files the standard way by invoking the gcc compiler. This method is suitable for smaller programs.

  • Using make and Makefiles.


Create a Program with gcc Compiler

Use the gcc compiler for simple programs only. Otherwise, use Makefiles when working with a large number of files.

To create a program with the compiler:

  1. Open the terminal and navigate to the directory containing the files.

  2. Invoke the

gcc compiler and type the name of both c files. The header doesn’t get compiled because it’s already included in c files.

gcc main.c text.c
  1. List all the files in the current directory with the

ls command:


The terminal shows that the new executable a.out file is created. The executable is also seen via a file explorer.

To test whether the compilation was successful, invoke the executable with:


The terminal shows that the executable works properly.


Create a Program with Make and Makefiles

Compiling files with make and Makefiles is simpler than using the compiler. Start by creating a new text document in the same directory and name it Makefile or makefile.

Open the file and use the basic Makefile syntax as the guideline.

Type the new executable’s name as the target, for example, my_app.

Add object files main.o and text.o as the dependencies. The make command recompiles the target every time object files change.

Hit TAB and invoke the gcc compiler for the object files:

<TAB> gcc main.o text.o

Add the -o flag and name the target my_app.

After writing the first rule, the Makefile looks like this:

my_app: main.o text.o
<TAB> gcc main.o text.o -o my_app

Next, instruct the Makefile on how to create main.o:

  1. Set

main.o as the target.

  1. Type in

main.c as the dependency. main.c serves to create and update main.o.

  1. Write the following command to update

main.o every time main.c changes:

gcc -c main.c

Add the -c flag to instruct the Makefile not to create a new executable but only to read the code and compile the object file.

main.o: main.c
<TAB> gcc -c main.c

To create text.o, set that file as the target, and add both text.c and text.h as dependencies. However, the gcc command only compiles the text.c file, since headers are never compiled:

text.o: text.c text.h
<TAB> gcc -c text.c

Save the Makefile and type make in the terminal.

The make command created two object files (main.o and text.o) and the executable (my_app).

To verify that make created new files, run ls again.

The terminal shows that running the command created my_app. To run the my_app file, type:



Update the Program

When one source file is changed, make only updates object files depending on that source file. For instance, to change the text displayed when running the my_app from “Learn about Makefiles” to “Where am I?”:

  1. Open

text.c in the text editor:

  1. Change the text to

“Where am I?”

Save the file, open the terminal, and run make.

The make command detected changes in text.c and recompiled only that file.

To verify the change, run the executable:



Compile All Files

To compile all files and not only the changed files, use -B or –always-make options.              

For example, to change the text in the text.c file back to “Learn about Makefiles” and save the file, enter:

make -B

The output shows that make compiled all the files in the folder, even the ones that haven’t been changed.


Clean Object Files

When a user runs make for the first time, the command creates object files and the executable. Therefore, to declutter the source folder and clean object files, add the clean function to the Makefile:

<TAB> rm *.o my_app

The command consists of:

  • The clean target with no dependencies – the target is always considered outdated and always executed.

  • The rm command – removes specified objects.

  • The *.o part – matches files with the o extension and cleans object files and my_app.

To clean object files, run:

make clean

After running ls again, the terminal shows that the object files and my_app have been removed.


Run make in Debug Mode

Run make in debug mode to print additional info about the compiling process. Execute make with the -d option to display the debugging output:

make -d


Use Different File as the Makefile

By default, make looks for a file called Makefile or makefile in the current directory. To use another file, run:

make -f [file_name]

For example, if a Makefile is named my_file, execute:

make -f my_file


Use Variables

Variables in Makefiles represent multiple file names, arguments, targets, dependencies, commands, source directories, or other items. Furthermore, a variable is defined by a name and represents a string of text called the variable’s value.

To define a variable, use =. For example, substitute gcc with a variable C.


my_app: main.o text.o
<TAB> $ (C) main.o text.o -o my_app

<TAB> $ (C) -c main.c
text.o: text.c text.h
<TAB> $ (C) -c text.c

When running make in the terminal, the command reads the C variable as gcc:



After going through the examples in this tutorial, you know how to use the make command in Linux and how it works.